By Vladislav Vashchenko,Mirko Scholz
This publication addresses key facets of analog built-in circuits and structures layout concerning process point electrostatic discharge (ESD) protection. it truly is a useful reference for a person constructing systems-on-chip (SoC) and systems-on-package (SoP), built-in with system-level ESD safeguard. The e-book makes a speciality of either the layout of semiconductor built-in circuit (IC) elements with embedded, on-chip process point safety and IC-system co-design. The readers may be enabled to convey the approach point ESD security options to the extent of built-in circuits, thereby decreasing or thoroughly taking away the necessity for extra, discrete elements at the published circuit board (PCB) and assembly system-level ESD specifications. The authors take a scientific method, in response to IC-system ESD safeguard co-design. a close description of the to be had IC-level ESD checking out equipment is equipped, including a dialogue of the correlation among IC-level and system-level ESD trying out tools. The IC-level ESD safety layout is proven with consultant case reports that are analyzed with quite a few numerical simulations and ESD checking out. the final technique for IC-system ESD co-design is gifted as a step by step approach that contains either ESD checking out and numerical simulations.
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