By Sven Goossens,Karthik Chandrasekar,Benny Akesson,Kees Goossens
This publication discusses the layout and function research of SDRAM controllers that cater to either real-time and best-effort functions, i.e. mixed-time-criticality reminiscence controllers. The authors describe the state-of-the-art, after which specialise in an structure template for reconfigurable reminiscence controllers that addresses successfully the fast evolving set of SDRAM criteria, when it comes to worst-case timing and gear research, in addition to implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA improvement board are used as an evidence of idea of the structure template.
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