By Steven H. Voldman

Electrostatic discharge (ESD) maintains to affect semiconductor elements and platforms as applied sciences scale from micro- to nano-electronics.

This e-book experiences electric overstress, ESD, and latchup from a whole-chip ESD layout synthesis strategy. It presents a transparent perception into the combination of ESD defense networks from a generalist point of view, via examples in particular applied sciences, circuits, and chips. Uniquely either the semiconductor chip integration concerns and floorplanning of ESD networks are lined from a ‘top-down' layout approach.

Look inside of for broad assurance on:

  • integration of cores, strength bussing, and sign pins in DRAM, SRAM, CMOS picture processing chips, microprocessors, analog items, RF parts and the way the combination impacts ESD layout and integration
  • architecturing of combined voltage, combined sign, to RF layout for ESD analysis
  • floorplanning for peripheral and middle I/O designs, and the results on ESD and latchup
  • guard ring integration for either a ‘bottom-up' and ‘top-down' technique addressing I/O safeguard earrings, ESD protect jewelry, I/O to I/O, and I/O to core
  • classification of ESD energy clamps and ESD sign pin circuitry, and the way to make the proper selection for a given semiconductor chip
  • examples of ESD layout for the cutting-edge applied sciences mentioned, together with CMOS, BiCMOS, silicon on insulator (SOI), bipolar expertise, excessive voltage CMOS (HVCMOS), RF CMOS, and clever power
  • practical equipment for the certainty of ESD circuit strength distribution, flooring rule improvement, inner bus distribution, present direction research, caliber metrics

ESD: layout and Synthesis is a continuation of the author's sequence of books on ESD defense. it really is an important reference for: ESD, circuit, and semiconductor engineers; layout synthesis workforce leaders; format layout, characterisation, floorplanning, attempt and reliability engineers; technicians; and groundrule and try out web site builders within the production and layout of semiconductor chips.

It is additionally beneficial for graduate and undergraduate scholars in electric engineering, semiconductor sciences, and production sciences, and on classes related to the layout of ESD units, chips and platforms. This e-book bargains an invaluable perception into the problems that confront smooth expertise as we input the nano-electronic era.

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